------
-- Technically this isn't a "true" stage, since it just contains combinatorial circuitary and isn't clocked. 
-- But the logic doesn't fit anywhere else, hence we have a separate block for this.
------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity WRITEBACK_UNIT is
	PORT(
	
	REG_WRITE_IN : in STD_LOGIC;
	MEM_TO_REG_IN : in STD_LOGIC;
	
	ALU_OUTPUT_IN : in STD_LOGIC_VECTOR(31 downto 0);
	DATA_MEM_IN : in STD_LOGIC_VECTOR(31 downto 0);
	
	VAL_WRITE_OUT : out STD_LOGIC_VECTOR(31 downto 0);
	REG_WRITE_OUT : out STD_LOGIC
	
	);

end WRITEBACK_UNIT;

architecture Behavioral of WRITEBACK_UNIT is
begin

	REG_WRITE_OUT <= REG_WRITE_IN;
	VAL_WRITE_OUT <= ALU_OUTPUT_IN when MEM_TO_REG_IN = '0' else DATA_MEM_IN when MEM_TO_REG_IN = '1';

end Behavioral;

